The present invention relates to integrated circuitry that can perform operations in parallel.
Hillis, U.S. Pat. No. 4,814,973, describes a parallel processor array that includes more than a million processor/memories interconnected in an n-dimensional pattern. The means for interconnecting the processor/memories includes means for generating an addressed message packet that is routed from one processor/memory to another in accordance with address information in the message packet. The interconnecting means also includes a synchronized routing circuit at each node for routing the message packets. As shown and described in relation to FIG. 1A, the array is connected in a two-dimensional grid pattern, which is useful for writing large amounts of data into the array, as at the beginning of a computation, and for reading out the array's contents when processing is interrupted. But for rapid interchange of data in random directions between processor/memories during computation, the integrated circuits (ICs), each containing 32 identical processor/memories, are also interconnected in a Boolean n-cube of fifteen dimensions, as described in relation to Tables I and II and as illustrated in FIGS. 2 and 3. Each IC is connected to its fifteen nearest neighbors by input lines and output lines, and each IC is provided with logic circuitry to control routing of messages, as described in relation FIGS. 6B and 8-16. Within each IC, bus connections are provided to the processor/memories so that every one of the more than one million processor memories can send a message to every other.